1. Field
Exemplary embodiments of the present invention relate to an amplifying circuit and a semiconductor memory device including the same for sensing and amplifying data transmitted between a local input/output line and a global input/output line.
2. Description of the Related Art
In general, data input/output lines are used for transferring data in semiconductor memory devices. Input/output lines for transferring data between data input/output pads and memory cells region are referred to as global data lines. A global data line is coupled to a plurality of banks that are located in a memory cell region. An output of a bit line amplifier is transferred from the memory cell region to a global data line via a local data line. Therefore, a circuit for transferring data between a global data line and a local data line is needed. With dynamic random access memory (DRAM), an input/output sense amplifier (IDSA) is used for transferring data from the local data line to the global data line during a read operation, and a write driver is used for transferring data from the global data line to the local data line during a write operation.
Semiconductor memory devices are always striving for larger storage capacity and lower operating voltages. In large capacity memory devices, there is increased load capacitance on data line pairs. As operating voltages continue to decrease, so do the differential in voltage differences between data line pairs. This decrease in differential voltage is making it more and more difficult for amplifying circuits to sense and amplify data coming from data line pairs.
Having a short RAS to CAS delay time (tRCD) is a key requirement for high speed semiconductor device operation. When minimizing RAS to CAS delay time (tRCD_min) for high speed operation, if bit line voltage levels are dropped and do not recover to a sufficient level, a pair of local input/output lines may not have enough potential difference to transmit and receive data properly. In other words, when a read command signal is applied after an active operation, the voltage level difference in the pair of local input/output lines is weakened because the bit line sense amplifier cannot operate properly. Therefore, a sense amplifying unit for sensing and amplifying minimum voltage level differences is needed. A multi stage amplifying scheme has been proposed to increase data transmission efficiency during high speed operations. A sense amplifying unit using a multi stage amplifying scheme amplifies data of a pair of local input/output lines in two stages. Since the multi stage amplifying operations are sequentially driven in response to separate strobe signals, offset characteristics of the input signal are improved. Therefore, small potential differences (e.g., 100 mv) in the pair of local input/output lines may be amplified and transferred to the global data line. That is, an input/output sense amplifying unit using a multi stage amplifying scheme may improve data transmission efficiency with a minimized RAS to CAS delay time tRCD_min, but it may also increase current consumption.